1. Field of the Invention
The present invention relates generally to directional couplers, and more particularly to a multi-layer chip directional coupler, in which a main signal line layer is formed on one dielectric layer, such that the main signal line layer is shorter than a coupling signal line layer formed on two dielectric layers, thus decreasing resistance of a conduction pattern and reducing insertion loss.
2. Description of the Prior Art
Recently, as mobile communication fields are rapidly developed, a usable frequency becomes higher and its bandwidth becomes narrower. Therefore, because parts adapted to such mobile communication devices must satisfy the requirements for high frequency and narrow bandwidth, required design conditions are more and more complicated.
A directional coupler used in the mobile communication devices serves to divide transmission signals at a constant rate. Especially, in the directional coupler, a certain amount of output signals from an amplifier of a transmission stage are sampled and transmitted to an automatic output controller, thus enabling an output signal having a constant output level to be transmitted through an antenna.
FIG. 1 is a view showing a conventional microstripline coupler. Referring to FIG. 1, in the microstripline coupler, a conductive metal is layered on a dielectric substrate 1 having a predetermined dielectric constant, such that a main signal line 3 and a coupling signal line 5 are formed to be spaced apart from each other. When signals are inputted to an input port of the coupler, most of the input signals are outputted through an output terminal. However, some part of the input signals are coupled to the coupling signal line 5, such that a coupling signal is generated by the coupling signal line 5, and outputted through a coupling port and an isolation port.
Generally, in the microstripline coupler having the above construction, coupling characteristics are decided according to a distance between the main signal line 3 and the coupling signal line 5 and their pattern shapes. Especially, the distance between the main signal line 3 and the coupling signal line 5 is a primary factor adjusted in the manufacturing process of the coupler. However, it is very difficult to accurately maintain the distance between the main signal line 3 and the coupling signal line 5 in the actual microstripline coupler.
Consequently, the conventional microstripline coupler is problematic in that it is very difficult to manufacture a coupler having highly coupled structure due to variation of the distance between the main signal line and the coupling signal line when the coupler is manufactured.
In order to solve the problem, a multi-layer chip directional coupler shown in FIG. 2 is proposed. Referring to FIG. 2, the multi-layer chip directional coupler is completely manufactured by forming electrode patterns on a plurality of dielectric layers and cohering the dielectric layers. As shown in FIG. 2, ground patterns 17a and 17b are respectively formed on the lowermost and uppermost dielectric layers 10a and 10f. Two dielectric layers 10b and 10c on which signal lines 13a and 13b are respectively formed are arranged in parallel with each other over the lowermost dielectric layer 10a. A via hole 20a is formed on the dielectric layer 10c, such that the signal lines 13a and 13b are connected to each other through the via hole 20a. 
Further, over the dielectric layer 10c, two dielectric layers 10d and 10e on which coupling signal lines 15a and 15b are respectively formed are arranged in parallel with each other. The coupling signal lines 15a and 15b are connected to each other through a via hole 20b formed on the dielectric layer 10e. In this case, both the main signal lines 13a and 13b, and the coupling signal lines 15a and 15b respectively formed on different two dielectric layers are symmetrically arranged as shown in FIG. 2. The dielectric layer 10f on which the ground pattern 17b is formed is arranged over the dielectric layer 10e, and a case 10g made of an insulating material is arranged over the dielectric layer 10f. Accordingly, the layers 10a to 10g are cohered to each other, such that the multi-layer chip directional coupler is completely manufactured.
In the conventional multi-layer directional coupler of FIG. 2, required coupling characteristics can be obtained by setting the distance between the main signal lines and the coupling signal lines around the dielectric layer 10d having a predetermined thickness. Further, the conventional multi-layer directional coupler of FIG. 2 is advantageous in that it can easily set the coupling characteristics by symmetrically manufacturing the main and coupling signal lines so as to form the patterns of the main and coupling signal lines to be the same, and it can simplify the manufacturing process of the coupler by symmetrically forming conduction patterns on each dielectric layer.
However, the conventional multi-layer chip directional coupler is problematic in that it has large insertion loss. The insertion loss is an amount of loss generated within a coupler chip except an amount of sampled signals in the coupler and output signals outputted through the main signal lines, and is a significant factor for defining the characteristics of the directional coupler. However, in the conventional multi-layer chip directional coupler having the symmetrical structure, because the main signal lines 13a and 13b are manufactured to have the same length as the coupling signal lines 15a and 15b, resistances are increased according to the length of the main signal lines 13a and 13b, thereby increasing the insertion loss.
Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and an object of the present invention is to provide a multi-layer chip directional coupler, in which a main signal line is asymmetrically formed to be shorter than a coupling signal line, thus simplifying the manufacturing process of the directional coupler, decreasing insertion loss.
In order to accomplish the above object, the present invention provides a multi-layer chip directional coupler, comprising a first ground pattern formed on the upper surface of a first dielectric layer; a coupling signal line formed of a conduction pattern on the upper surface of a second dielectric layer formed over the first dielectric layer; a main signal line formed of a conduction pattern on the upper surface of a third dielectric layer formed over the second dielectric layer, the main signal line being shorter than the coupling signal line; a second ground pattern formed on the upper surface of a fourth dielectric layer formed over the third dielectric layer; and a plurality of ports formed on the side surfaces of the first to fourth dielectric layers and connected to the main signal line, the coupling signal line, and the first and second ground patterns.
According to a preferred embodiment, the second or third dielectric layer can be comprised of a plurality of dielectric layers. In this case, conduction patterns forming the coupling signal line or the main signal line respectively formed on the upper surface of the second or third dielectric layer are connected to each other through a via hole penetrating through a plurality of dielectric layers to be one line.
According to another preferred embodiment, preferably the length of the main signal line is set to be approximately half that of the coupling signal line so as to reduce insertion loss.